(1) Field of the Invention
The present invention relates to a semiconductor integrated circuit device in which a delay locked loop DLL circuit is provided.
With high speed and high integration of recent semiconductor integrated circuit devices, such as an SDRAM, it is important to stably supply an internal clock which phase is synchronized to an external clock to an internal circuit of the semiconductor integrated circuit device. A semiconductor integrated circuit device utilizes a delay locked loop DLL circuit to produce an internal clock which phase is synchronized to an external clock for supplying control signals to the internal circuit in synchronism with the internal clock. The DLL circuit acts to adjust a timing of the supply of the internal clock with high accuracy.
In addition, with high speed and high integration of recent semiconductor integrated circuit devices, the power consumption is likely to increase. To avoid this, there is a demand for a semiconductor integrated circuit device able to work with a low level of power consumption.
(2) Description of the Related Art
A description will now be given of a conventional SDRAM in order to give an example of a conventional semiconductor integrated circuit device.
Suppose that the conventional SDRAM can be set in an "active power-down" state. If the conventional SDRAM is set in the active power-down state, all external clocks, subsequently supplied to the conventional SDRAM from the external element are made invalid.
FIG. 19 shows a control signal generator provided in a conventional SDRAM. As shown in FIG. 19, in the conventional SDRAM, data is written to or read from a DRAM CORE (not shown) in synchronism with an internal clock (INT CLK).
In the control signal generator of FIG. 19, an external clock (EXT CLK), which is externally supplied to the conventional SDRAM, and an externally controlled clock enable signal (CKE) are input to an AND gate 301, and the AND gate 301 outputs an internal clock (INT CLK) which is to be supplied to a plurality of latches 302 through 305 and an internal circuit 306 of the conventional SDRAM. When the CKE at the input of the AND gate 301 is set at a high (H) level, the INT CLK output by the AND gate 301 is supplied to the latches 302 through 305 and the internal circuit 306. When the CKE is set at a low (L) level, the AND gate 301 does not output the INT CLK, and the supply of the INT CLK to the elements of the conventional SDRAM is inhibited.
When the CKE is set at the L level and control signals at the input of the control signal generator are set in a predetermined condition, the SDRAM is set in the active power-down state. Hereinafter, the predetermined condition will be called the active power-down setting condition. The above-mentioned control signals are, for example, a chip select (CS) signal, a row address select (RAS) signal, a column address select (CAS) signal and a write enable (WE) signal which are supplied to the latches 302, 303, 304 and 305, respectively.
In the control signal generator of FIG. 19, the control signals are retained by the latches 302-305 in synchronism with the INT CLK. Further, the retained control signals LATCH CS, LATCH RAS, LATCH CAS and LATCH WE are supplied from the latches 302-305 to the internal circuit 306 in synchronism with the INT CLK. The internal circuit 306 includes other elements of the conventional SDRAM, different from the AND gate 301 and the latches 302-205. For example, the internal circuit 306 may include the DRAM CORE and a command decoder (which acts to determine whether the active power-down setting condition is satisfied).
FIG. 20 is a time chart for explaining an operation of the control signal generator of the conventional SDRAM of FIG. 19. In FIG. 20, T1 indicates a time a rising edge of the EXT CLK occurs, and T2 indicates a time a falling edge of the CKE occurs.
As shown in FIG. 20, when the CKE is at the H level and the EXT CLK is set from the L level to the H level (or at the rising edge) at the time "T1", the INT CLK output by the AND gate 301 is set at the H level with a certain delay. That is, a rising edge of the INT CLK occurs after the certain delay from the rising edge of the EXT CLK. In synchronism with the rising edge of the INT CLK, the control signals CS, RAS, CAS and WE are retained by the latches 302, 303, 304 and 305, and all the retained control signals LATCH CS, LATCH RAS, LATCH CAS and LATCH WE are set at the H level. That is, the conventional SDRAM is set in the active state.
Further, as shown in FIG. 20, when the CKE is set at the L level at the time T2 (during the active state), the active power-down setting condition of the conventional SDRAM is satisfied. The conventional SDRAM at this time is set in the active power-down state. That is, the EXT CLK is made invalid. In the conventional SDRAM, when it is set in the active power-down state, supplying the INT CLE to the latches 302-305 and the internal circuit 306 is inhibited. The control signals supplied to the latches 302-305 are disregarded with no regard as to whether the control signals are set at the H level or the L level, as indicated by the shaded lines in FIG. 20. The latches 302-305 are held in the conditions that are the same as those before the active power-down state of the conventional SDRAM starts.
In the conventional SDRAM, the latches 302-305 are continuously held in the previous conditions until the active power-down state is terminated or canceled. That is, the latches 302-305 remains in the previous conditions until the CKE is set at the H level and the operation of the INT CLK is started.
However, if the working frequency of a the conventional SDRAM is increased, the time the INT CLK is set at the H level or the L level in response to the level of the EXT CLK is considerably delayed. In such a case, the conventional SDRAM is likely to malfunction due to a delay of the INT CLK relative to the EXT CLK.